Wafer level interposer

ABSTRACT

Double-sided interposer assemblies and methods for forming and using them. In one example of the invention, an interposer comprises a substrate having a first surface and a second surface opposite of said first surface, a first plurality of contact elements disposed on said first side of said substrate, and a second plurality of contact elements disposed on said second surface of said substrate, wherein said interposer connects electronic devices via said first and said second plurality of contact elements.

FIELD OF THE INVENTION

[0001] The present invention generally relates to wafer levelinterposers, and more particularly to interposers having double-sidedcontact elements for interfacing two electrical devices, and to methodsfor making such interposers.

BACKGROUND OF THE INVENTION

[0002] There are numerous interposers and methods for making and usingthese interposers in the prior art. Interposers are used for differentpurposes. Generally, interposers provide an interface between twoelectrical components, such as one or more semiconductor devices and aprinted circuit board, or two printed circuit boards. For example, aninterposer can be used to interface a semiconductor wafer to a probecard for testing of the dies on the wafer to determine which dies aregood. A wafer tester or prober may be advantageously employed to make aplurality of discrete pressure connections to a like plurality ofdiscrete contact elements (e.g. bonding pads) on the dies. In thismanner, the semiconductor dies can be tested, for example, to determinewhether the dies are non-functional or partially functional (each, “bad”die), prior to singulating the dies from the wafer.

[0003] Testing of semiconductor devices is performed on various levels.For example, in very advanced systems, semiconductor devices may betested for performance operations, while still in wafer form, undervarious temperature and environmental conditions. This type of testingis commonly referred to as “wafer level test.” Referring to FIG. 1, atest assembly 100 is shown to illustrate a technique for performingwafer-level test and/or wafer level burn-in of semiconductor devicesincluded in a test substrate (application specific integrated circuits(ASIC) 106 and base plate 108, collectively) having active electroniccomponents such as ASICs 106 a-106 d, mounted to an interconnectionsubstrate or incorporated therein. See commonly assigned U.S. Pat. No.6,064,213 entitled “Wafer-Level Burn-In and Test”, which is hereinincorporated by reference as though set forth in full. Spring contactelements 110 effect interconnections between the ASICs 106 a-106 d(ASICs 106 a-106 d generally comprise the ASICs 106) and a plurality ofdevices-under-test (DUTs), 102 a-102 d, on a wafer-under-test (WUT) 102.In one embodiment, the assembly is disposed in a vacuum vessel withindependent temperature regulation so that the ASICs can be operated attemperatures independent from and in many instances significantly lowerthan the burn-in temperature of the DUTs. The spring contact elements110 may be mounted to either the DUTs 102 a-102 d or the ASICs 106 a-106d, and may fan out to relax tolerance constraints on aligning andinterconnecting the ASICs 106 and the DUTs 102. For the connection 120to the host controller, a significant reduction in interconnect countand consequent simplification of the interconnection substrate isrealized because the ASICs are capable of receiving a plurality ofsignals for testing the DUTs over relatively few signal lines from ahost controller 116 and promulgating these signals over the relativelymany interconnections 110 between the ASICs 106 and the DUTs 102. TheASICs 106 can also generate at least a portion of these signals inresponse to control signals from the host controller 116. Physicalalignment techniques are also described in the reference.

[0004] During testing, a power supply 118 provides power signals to theASICs through a base plate 108 connected to an upper portion of a chuck104 a used for holding the test assembly in place with the assistance ofguide pins 112. While operational, i.e. under test, force is applied inthe z-direction bringing the ASICs 106 in contact with the springcontact element 610 and compressing the latter to a position determinedby compression stops 114, which are positioned at either end of thewafer 102. The compression stops function to stop the base plate 108from moving down in the z-direction thereby determining the extent towhich the spring contact elements 110 are compressed and thus avoidingover-compression of the latter.

[0005]FIG. 2 illustrates an alternative test assembly 200 including awafer 202, an interposer 204 and a tester contactor 206. On bothsurfaces of the interposer, solder balls 210 are formed in order tointerconnect wafer 202 to tester contactor 206. The contact pads 208 onwafer 202 come in contact with solder balls 210 on the top surface ofinterposer 204 when wafer 202 is lowered toward tester contactor 206.Upon further lowering of wafer 202, solder balls 212 on the bottomsurface of interposer 204 come in contact with the contact pads 214 ofthe tester contactor 206, thereby establishing electrical connectionbetween wafer 202 and the tester through tester contactor 206.Typically, a wafer can have in excess of 10,000 contact pads. Forinstance, a 200 mm wafer may have 20-50 thousand contact pads. Toestablish reliable connections between such a large number of contactpads between the wafer and the tester is a significant challenge.

[0006] In prior art wafer-level testing techniques, the interconnectionelements reside on the wafer or the contactor (wiring layer). While thisprior art approach provides certain advantages, it also has certainlimitations. For example, when the interconnection elements or springsreside on the wafer or contactor, a modular construction approach cannotbe implemented for a burn-in system. Similarly, the use of solder ballson the interposer does not permit a modular construction.

[0007] It is noted that there are certain existing double-sidedinterconnection substrates, such as shown in commonly assigned U.S. Pat.No. 5,917,707, entitled “Flexible Contact Structure With An ElectricallyConductive Shell” (for example, FIG. 36), and commonly assigned U.S.patent application Ser. No. 08/452,255, entitled Electrical ContactStructures Formed By Configuring A Flexible Wire To Have A SpringableShape And Covercoating The Wire With At Least One Layer Of A ResilientConductive Material, Methods Of Mounting The Contact Structures ToElectronic Components, And Applications For Employing The ContactStructures” (for example, FIG. 39). These prior art substrates, however,do not address completely certain wafer-level testing needs.

[0008] A need therefore exists for an improved interposer and a methodfor making and using the same without the need to connect resilientinterconnect elements or other types of interconnect elements onto theDUT and/or the device being packaged.

SUMMARY OF THE INVENTION

[0009] The present invention provides a method for testing asemiconductor device wafer comprising connecting a first side of aninterposer having a first plurality of resilient contact elementsdisposed thereon to the wafer, connecting a second side of an interposerhaving a second plurality of resilient contact elements disposed thereonto a wiring layer and providing a pathway for signals from the wafergoing to and from the wiring layer thereby permitting exercising ofdevices on the wafer.

[0010] A method of the present invention also enables performingwafer-level burn-in and test of a plurality of semiconductor devices(DUTs) resident on a semiconductor wafer. This includes providing aplurality of active electronic components having terminals on a surfacethereof and providing an interposer for effecting direct electricalconnections between terminals of the plurality of DUTs and the terminalsof the active electronic components.

[0011] In another embodiment of the present invention, a method isprovided for forming an interposer by providing a substrate having afirst surface and a second surface, the second surface being opposite ofthe first surface, forming a first plurality of contact elements on thefirst surface of the substrate and forming a second plurality of contactelements on the second surface of the substrate.

[0012] A test assembly in accordance with the present inventioncomprises a wiring substrate having a first surface, a second surfaceand a plurality of contact terminals on the first surface thereof, aninterposer having a first surface, a second surface, a plurality ofcontact pads disposed on the first and the second surface thereof, and afirst plurality of resilient contact structures mounted adjacent to andextending from the first surface thereof and a second plurality ofresilient contact structures mounted adjacent to and extending from thesecond surface thereof. The interposer provides electrical connectionbetween the wiring surface and the wafer by engaging the contact pads ofthe wiring surface with the first plurality of resilient contactstructures and the contact pads of the wafer with the second pluralityof resilient contact structures.

[0013] Various other assemblies and methods are described below inconjunction with the following figures.

BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The present invention is illustrated by way of example and notlimitation in the figures of the accompanying drawings in which likereferences indicate similar elements.

[0015]FIG. 1 shows a prior art test assembly for performing wafer-levelburn-in and testing of semiconductor devices included on a testsubstrate.

[0016]FIG. 2 illustrates a prior art test assembly including aninterposer with solder balls attached to both surfaces thereof.

[0017]FIG. 3a shows an interconnect assembly including an interposerwith compression stops in accordance with an embodiment of the presentinvention.

[0018]FIG. 3b shows an interconnect assembly including a freely floatinginterposer without any compression stops in accordance with anembodiment of the present invention.

[0019]FIG. 4a shows an interposer with identical set of resilientcontact elements on both surfaces thereof, but also includingdisplacement of contacts so that the relationship between upward anddownward contacts is not 1:1 in accordance with an embodiment of thepresent invention.

[0020]FIG. 4b shows an interposer with different sets of resilientcontact elements on both surfaces thereof, according to the presentinvention but including pitch spreading from one set of resilientcontacts to the other.

[0021]FIG. 4c shows an interposer including passive components on thelower surface of the interposer substrate in accordance with anembodiment of the present invention.

[0022]FIG. 4d shows an interposer including components on both sides ofthe interposer substrate in accordance with an embodiment of the presentinvention.

[0023]FIG. 5 is a cross-sectional view of an embodiment of a genericspace transformer in accordance with an embodiment of the presentinvention.

[0024]FIGS. 6a-6 f are side cross-sectional views illustratingfabricating capture pads that are hourglass-like through-holes in asubstrate in accordance with an embodiment of the present invention.

[0025]FIG. 6g is a schematic illustration of a step in the processdescribed with respect to FIGS. 6a-6 f in accordance with an embodimentof the present invention.

[0026]FIG. 6h is a schematic illustration of an alternate step in theprocess described with respect to FIGS. 6a-6 f in accordance with anembodiment of the present invention.

[0027]FIG. 6i is a side cross-sectional view of a socket substrate thathas been made using the procedure set forth in FIG. 6h in accordancewith an embodiment of the present invention.

[0028]FIG. 7a is a side view of an electronic component being joinedwith tip structures in accordance with an embodiment of the presentinvention.

[0029]FIG. 7b is a side view of a further step in joining an electroniccomponent with tip structures in accordance with an embodiment of thepresent invention.

[0030]FIG. 8a is a side, cross-sectional view of an embodiment whereinthe contact tip structures of the present invention are affixed to atype of elongate interconnection elements in accordance with anembodiment of the present invention.

[0031]FIG. 8b is a perspective view of a contact tip structure, whichhas been joined to an interconnection element in accordance with anembodiment of the present invention.

[0032]FIG. 8c is a perspective view of a contact tip structure joined toan end of an interconnection element in accordance with an embodiment ofthe present invention.

[0033]FIG. 9a shows an interconnect assembly including an interposerhaving a plurality of passive and/or active elements in accordance withan embodiment of the present invention.

[0034]FIG. 9b shows an interconnect assembly including an assemblyhaving a plurality of passive and/or active elements mounted on the dieand the wafer contactor in accordance with an embodiment of the presentinvention.

[0035]FIGS. 10a and 10 b are side cross-sectional and perspective views,respectively, of a completed contact structure formed on an electroniccomponent in accordance with an embodiment of a process for making acontact structure.

[0036]FIG. 11 shows an interposer having disposed a set of solder ballson one of its surfaces for interconnecting to another electroniccomponent in accordance with an embodiment of the present invention.

[0037]FIG. 12 shows an interposer having disposed on one of its surfacesa plurality of spring contact elements that are fabricated rather thancomposite in accordance with an embodiment of the present invention.

[0038]FIG. 13 shows an interposer interconnecting two sets of tilesubstrates in accordance with an embodiment of the present invention.

[0039]FIG. 14 shows an interposer wherein two different types of contactelements are employed on the top and bottom surfaces of the interposerin accordance with an embodiment of the present invention.

[0040]FIG. 15 shows an interconnect assembly including an interposerwith the implementation of a pressure actuated contactor in accordancewith an embodiment of the present invention.

[0041]FIG. 16 shows an interposer interconnecting a plurality of DUTs toa plurality of ASICs in accordance with an embodiment of the presentinvention.

[0042]FIG. 17 shows an interconnect assembly including a hostcontroller, a power supply and a vacuum vessel in accordance with anembodiment of the present invention.

[0043]FIG. 18a shows an interposer comprising a substrate and variousbeam-type resilient contact elements in accordance with an embodiment ofthe present invention.

[0044]FIG. 18b shows an interposer assembly including contact elementsand compression stops in various positions in accordance with anembodiment of the present invention.

DETAILED DESCRIPTION

[0045] The present invention relates to an interposer having resilientinterconnect elements disposed upon two surfaces of a substrate forcontacting a wafer having a plurality of dies disposed thereupon, and totechniques for fabricating such an interposer. As will be evident fromthe description that follows, techniques of fabricating an interposerinvolve fabricating interconnect elements directly upon the interposersubstrate, or transferring elements of them to the interposer substrate,making connections with sets of interconnect elements for contacting thesemiconductor devices while they are a part of the wafer. The interposeris useful for connecting two electronic components generally, and forperforming testing, exercising and burn-in in particular. The followingdescription and drawings are illustrative of the invention and are notto be construed as limiting the invention. Numerous specific details aredescribed to provide a thorough understanding of the present invention.However, in certain instances, well-known or conventional details arenot described in order to not unnecessarily obscure the presentinvention in detail.

[0046] Certain terms are utilized throughout this document and as suchare intended to have the meanings provided below:

[0047] The terms “cantilever” and “cantilever beam” are used to indicatethat an elongate structure is mounted (fixed) in one region, withanother region free to move, typically in response to a force actingwith a component transverse to the longitudinal axis of the elongatestructure.

[0048] The term “resilient”, as applied to contact structures orinterconnection elements, indicates structures that exhibit primarilyelastic behavior in response to an applied load. The free-standing,resilient interconnection elements of the present invention are aspecial case of either compliant or resilient contact structures.

[0049] The term “electronic component” includes, but is not limited to:interconnect and interposer substrates; semiconductor wafers and diesmade for example of any suitable semiconducting material such as silicon(Si) or gallium-arsenide (GaAs); interconnect sockets; test sockets;sacrificial members, elements and substrates, semiconductor packages,including ceramic and plastic packages, chip carriers; passivecomponents such as resistors or capacitors, and connectors.

[0050] Turning to address the present invention in detail, FIGS. 3a and3 b illustrate exemplary interconnect assemblies. The interconnectassembly 1000 is shown to include an interposer 1002. Interposer 1002includes a substrate 1004 with a first surface and a second surface uponeach of which surfaces are disposed a plurality of resilient contactelements, 1006 and 1008. In FIG. 3a, an interposer 1002 establishescontact between a wafer 1012 and a wafer contactor 1010 through pressurecontacts applied to the contact elements 1006 and 1008. Wafer 1012 issecured to a base support 1016 and the housing assembly 1018 supportscontactor 1010. As shown in FIG. 3a, substrate 1004 has disposedthereupon one or more compression stops 1014 for preventingover-compression of the resilient contact elements 1006 and 1008, aswill be explained more fully in the discussion herein below.

[0051] While a single compression stop 1014 will function to preventover-compression, it is preferred to have a plurality of compressionstops disposed on substrate 1004. The height of the compression stops ispredetermined in order to define a first position when the resilientcontact elements are in mechanical and electrical contact with anothercontact elements. In one embodiment of the present invention, there isno need for compression stops on the bottom surface of substrate 1004since the rigid supports 1020 limit excessive movement of wafer 1012. Itshould be understood that compression stops similar to 1014 can beprovided on the bottom of interposer 1002 to protect the resilientcontact elements 1006.

[0052] In operation, pressure contact is applied to wafer 1012 movingthe latter in the z-direction toward wafer contactor 1010, therebymeeting and then compressing resilient contact elements 1008. Whencontact elements 1008 are compressed, resilient contact elements 1006are also compressed thereby establishing mechanical contact between theterminals of wafer 1012 and the terminals of the wafer contactor 1010.It should be noted that the terminals of wafer 1012 and wafer contactor1010 are not shown in FIG. 3a. Compression stops 1014 preventover-compression and thereby prevent damage of resilient contactelements 1008.

[0053] In general, a conformal or flexible substrate may be used assubstrate 1004 for performing wafer-level contacting or other types ofapplication discussed herein or known to those skilled in the art. Theuse of a conformal substrate permits for compensation of non-flatness inan over all assembly of the type shown in FIG. 3a.

[0054]FIG. 3b shows an alternative embodiment of an interconnectassembly 1030 including an interposer 1032, a wafer 1050 supported on abase 1044 and a wafer contactor 1036. Wafer contactor 1036 is supportedin housing assembly 1034. Interposer 1032 comprises a substrate 1040 anda plurality of contact elements 1046 on the top of substrate 1040, andanother set of contact elements 1048 attached to the bottom of substrate1040.

[0055] Interposer 1032 is a fully floating interposer, which ispositioned away from all stops or supports once fully assembled.Resilient contact elements 1046 and 1048 provide opposing forces (fromwafer contactor 1036 and wafer 1050, respectively) in order to maintainthis position. The excessive movement of interposer 1032 toward eitherwafer 1050 or wafer contactor 1036 is arrested by placement constraints1042 and 1038, respectively. In this instance, the addition of stopssimilar to 1014 of FIG. 3a may be necessary to control the deformationof the substrate at a point away from the locating structures 1042 and1038.

[0056] Substrate 1004 (of FIG. 3a) or 1040 (of FIG. 3b) may be made ofmany materials, including for example, an organic dielectric such asprinted circuit board (PCB) materials, silicon, insulator coated metalsheeting, metal matrix composites, glasses or ceramics. In certainapplications, it would be desirable to form the substrate 1004 fromsilicon. This is particularly helpful in an assembly, which will be inclose contact with an operating semiconductor device. Such devicesgenerally become warm during use, or perhaps during testing, and it isvery helpful to connect to materials which have a similar coefficient ofthermal expansion so the active device and the contactor remain in asimilar geometrical relationship. Matching a silicon device to anothersilicon devise is particularly desirable.

[0057]FIG. 4a shows an interposer 1052 wherein the resilient contactelements 1054 on the top surface of the substrate 1056 are similar inconstruction but displaced laterally with respect to the resilientcontact elements 1058 on the bottom surface of the substrate 1056. Alsoshown in FIG. 4a are conducting traces 1060 through which electricalcontact is established between the resilient contact elements on the topand bottom surfaces of the substrate. FIG. 4b shows a differentembodiment of an interposer 1062. The resilient contact elements 1064 onthe top surface of the interposer are shown to be constructeddifferently and at a different lateral separation than the resilientcontact elements 1066 on the bottom surface of interposer 1062. In theinterposer of FIG. 4b, the lower surface of interposer 1062 may contacta standard electronic device such as a contactor while the upper surfaceof interposer 1062 is customized to mate with a specific electronicdevice. Accordingly, different designs of the contact elements mountedon an interposer as described hereinabove fall within the scope andspirit of the present invention. Such designs enable different types ofelectronic components to be interconnected.

[0058]FIG. 4c shows an alternative embodiment of an interposer 1068. Theresilient contact elements 1070 on the top surface of interposer 1068are shown to be connected in a not 1:1 relationship with those elements1072 on the bottom surface 1074 of the interposer. In FIG. 4c theinterposer substrate may contain wiring layers for power and grounddistribution, allowing coupling of signals between multiple devices onthe wafer under test, etc. Additionally, passive or active components1076 may be attached to bottom surface 1074. Alternatively, techniquesknown in the art for placing passive components such as resistors,capacitors or inductors, within the wiring substrate 1068, e.g.“embedded passives” may be used.

[0059]FIG. 4d shows a different embodiment of an interposer 1078.Resilient contact elements 1080 on the top surface 1082 of interposer1078, as well as resilient contact elements 1084 on the bottom surface1086 of interposer 1078 are shown to be respectively connected topassive or active components 1088 and 1090, which are attached to (oralternatively, though not shown, may be embedded in) the interposersubstrate. Capacitive elements for decoupling and/or resistive elementsfor isolation or termination may be included with the interposersubstrate. Resilient contact elements 1092 and 1094 are also located onthe top surface 1082 and bottom surface 1086 of interposer 1078 toenable electrical connection of the substrate for contactingsemiconductor devices.

[0060] By way of further explanation, in one type of an interposer, theposition of the contact elements located on the top surface of theinterposer (e.g., as discussed in connection with FIG. 3a, contactelements 1008) are essentially directly above the position of thecontact elements located on the bottom surface of the interposer (inFIG. 3a, contact elements 1006). In alternative embodiments (e.g., inFIG. 4b), the positions of the top and bottom contact elements of aninterposer may not be aligned vertically. For example, correspondingcontacts may be at identical x-y coordinates, with different z valuesrelative to the interposer. In alternative embodiments, contact elementsof an interposer are re-positioned so that there is correspondence butdifferent spacing between the location of the “top” and the location ofcorresponding “bottom” contact elements.

[0061] It should also be appreciated that the interposer may alsofunction as a space transformer, to translate one pitch (distance fromone contact element to another) to another pitch on respective faces ofthe substrate. In FIG. 5, a space transformer 1100 is shown wherein thedesired space-transforming is accomplished by the substrate 1102 of thespace transformer. Alternatively, or in addition to this repositioning,it is possible to shape or position the individual resilient contactstructures (not shown) attached thereto. (More detail is provided inFIG. 23 and discussions relating thereto of U.S. Pat. No. 5,917,707,entitled “Contact Structure for Interconnections, Interposers,Semiconductor Assembly,” the disclosure of which is incorporated hereinby reference as though set forth in full).

[0062] Space transformer substrate 1102 has a top (as viewed) surface1102 a and a bottom (as viewed) surface 1102 b and is preferably formedas a multi-layer component having alternating layers of insulatingmaterial (e.g., ceramic) and conductive material. In this example, onewiring layer is shown as including two (of many) conductive traces 1104a and 1104 b.

[0063] A plurality (two of many shown) of terminals (contact pads) 1106a and 1106 b are disposed on top surface 1102 a of space transformersubstrate 1102 at a relatively fine pitch (relatively close to oneanother). A plurality (two of many shown) of terminals (contact pads)1108 a and 1108 b are disposed on bottom surface 1102 b of spacetransformer substrate 1102 at a relatively coarse pitch (relative toterminals 1106 a and 1106 b); i.e., further apart from one another). Forexample, bottom terminals 1108 a and 1108 b may be disposed at about50-100 mil or 1.2-2.5 millimeter pitch (comparable to printed circuitboard pitch constraints), and top terminals 1106 a and 1106 b may bedisposed at about 1-10 mil or 0.025-0.250 millimeter pitch (comparableto the center-to-center spacing of semiconductor die bond pads),resulting in a 50:1 pitch-transformation. Top terminals 1106 a and 1106b are connected to the corresponding bottom terminals 1108 a and 1108 b,respectively, by associated conductors 1110 a/1112 a and 1110 b/1112 b,respectively, connecting the terminals to the conductive traces 1104 aand 1104 b, respectively. This is all generally well known, in thecontext of multi-layer land grid array (LGA) support substrates, and thelike. For a more detailed discussion of space transformers, the readeris directed to U.S. Pat. No. 5,974,662, entitled “Method of PlanarizingTips of Probe Elements of a Probe Card Assembly,” issued on Nov. 2,1999, the disclosure of which is herein incorporated by reference asthough set forth in full. Alternatively, an interposer of the presentinvention may include a different pad pattern on one surface (i.e. “top”surface) than the other surface (i.e. “bottom” surface) with or withouta change in pitch.

[0064] In the case of the use of semiconductors, through-holes are madethrough the semiconductor device for connection of the correspondingcontact elements. Commonly assigned U.S. patent application Ser. No.09/205,502 entitled “Socket For Mating With Electronic Component,Particularly Semiconductor Device With Spring Packaging, For Fixturing,Testing, Burning-In or Operating Such A Component”, the disclosure ofwhich is incorporated herein as though set forth in full, discussesmaking such through-holes. In this application, particular attention isdirected to FIGS. 4a-4 f, which are presented herein as FIGS. 6a to 6 f.

[0065]FIGS. 6a to 6 f show side cross-sectional views illustratingfabricating hourglass-like through holes in a semiconductor substrate.FIG. 6a illustrates a first step of the process of one embodiment of thepresent invention. A layer 1204 of nitride is applied to a front surfaceof a substrate 1202 which is a piece of 1,0,0 silicon. The layer ofnitride is patterned to have openings 1206. These openings 1206 may besquare, having cross-dimensions (S1) of about 150-250 μm, such as about200 μm. In a similar manner, a layer 1208 of nitride is applied to aback surface of the substrate 1202 and is patterned to have openings1210. Openings 1210 in the nitride layer 1208 may be square, havingcross-dimensions (S2) of about 150-250 μm, such as about 200 μm.Selected ones and in general, each, of openings 1206 is located directlyopposite a corresponding one of openings 1210. A pair of alignedopenings 1206 and 1210 will determine the location of a through-holeterminal formed in silicon substrate 1202. Openings 1206 and 1210 areillustrated as having the same cross-dimension as one another (i.e.,S1=S2), but as will be discussed herein below, this is not necessary andmay not be preferred in some implementations.

[0066] In one preferred embodiment, openings equivalent to openings 1206and 1210 are rectangular rather than square. Opposing openings can haverectangles oriented in parallel, or opposing openings could beorthogonal. In general, a rectangular opening will create a troughstructure rather than a point when etched. The relative dimensions ofeach need not be the same.

[0067]FIG. 6b illustrates a next step wherein the substrate 1202 isetched within openings 1206 and 1210, nitride layers 1204 and 1208acting as masking material to prevent etching other than at openings1206 and 1210. A suitable etchant is potassium hydroxide (KOH). Othersuitable etching agents include NaOH and strong bases. A feature of1,0,0 silicon is that it will etch in a strong base solution at anangle, the angle being 53.7°. The etch proceeds according to the crystallattice of the silicon. Thus, it is preferred that openings 1206 and1210 be oriented to align with the crystal lattice. The orientation ofthe lattice is known and generally indicated by a notch in the generallycircular wafer of silicon.

[0068] Etching from only one side may give a pyramid shaped pitextending into that side of the substrate if the etching process isstopped prior to reaching a pointed pyramidal feature. The dimensions ofthe pit are controlled by the dimension and orientation of the openingwithin which the etching occurs, and the etch angle of 1,0,0 silicon.The etching comes to a halt when there is no remaining exposed siliconon the surface of the substrate. In general, starting with a squareopening, a pyramid-shaped pit is created. If the etch is not driven tocompletion, a truncated pyramid can be formed. Where the opening foretching is rectangular, a trough structure will be formed.

[0069] In a preferred embodiment, etching is from both sides, and twopyramid-shaped pits 1212 and 1214 (as shown in FIG. 5b) “grow” towardone another. By ensuring that the openings are sufficiently wide, andthe substrate is sufficiently thin, pyramid-shaped pits 1212 and 1214will grow into one another (overlap), resulting in the“hourglass-shaped” through-holes illustrated in FIG. 6b. If desired, thepits may be allowed to “over-etch” so that nitride layers 1204 and 1208slightly overhang the pit openings. Once etching is done, nitride layers1204 and 1208 may be removed, by preferential etching.

[0070] Etching this hourglass forms a “via” in the silicon substrate.Vias are widely used in many electronic products such as semiconductordevices and multilayer substrates. This new via will be madeelectrically conducting, then can be used in many of the ways known forusing vias.

[0071]FIG. 6c illustrates a next step wherein substrate 1202 isre-nitrided, such as by thermally growing a very thin layer 1216 ofnitride on all the surfaces of substrate 1202, including within thesidewalls of pits 1212 and 1214. This nitride functions in part toinsulate the body of the semiconductor substrate from any subsequentlyapplied conductive material. Alternatively, a layer of silicon oxide, orother organic or inorganic insulating coating may be applied to thesubstrate.

[0072]FIG. 6d illustrates a next step wherein the entire substrate 1202is coated (e.g., sputter-coated) with a thin layer 1218 oftitanium-tungsten (TiW), then a thin seed layer 1210 of gold (Au).Representative dimensions and useful methods and materials are set forthin detail in co-pending, commonly assigned U.S. patent application Ser.No. 09/032,473, filed Feb. 26, 1998, entitled “Lithographically DefinedMicroelectronic Contact Structures,” the disclosure of which isincorporated herein by reference as though set forth in full.

[0073]FIG. 6e illustrates a next step wherein layer 1230 of maskingmaterial, such as photoresist, is applied to both sides of substrate1202 and patterned to have openings aligned with pits 1212 and 1214. Theseed layer 1220 within the pits is not covered by the masking material.Then, one or more layers of a conductive material 1232, such as nickel,copper or gold, is deposited, such as by plating, onto exposed seedlayer 1220 within pits 1212 and 1214.

[0074]FIG. 6f illustrates a next (final) step wherein masking layer 1230is removed (such as by rinsing off), and the unplated part of seedlayers 1218 and 1220 are removed (such as by selective chemicaletching), leaving conductive material 1232 within and bridging pits 1212and 1214, thereby forming a conductive via through substrate 1202. Thisprovides electrical continuity between pit 1212 and pit 1214. At thesame time as the vias are metallized, traces may be patterned on theopposing faces of the substrate to allow for more functionality orredistribution. Further details of an interposer substrate withthrough-hole type terminal can be found in the aforementioned U.S.patent application Ser. No. 09/205,502.

[0075]FIG. 6g illustrates an interim temporal step in the process justdescribed. When pits 1212 and 1214 (see FIG. 6b) are first being etched,they “grow” towards one another. In the case that openings 1206 and 1210(see FIG. 6a) have the same cross-dimension (both are “S1”), the growingpits should be symmetrical with one another, one being the mirror imageof the other, as illustrated.

[0076]FIG. 6h illustrates an interim temporal step (compare FIG. 6g) inthe process, in a case where openings 1206 and 1210 (see FIG. 6a) do nothave the same cross-dimension, for example, opening 1206 has a largercross dimension than opening 1210 (i.e., S1/S2). Here, it can beobserved that pits 1244 and 1246 (compare 1212 and 1214) grow intosubstrate 1242 (compare 1202) at the same rate, but that pit 1246 hasreached its apex and terminated its growth.

[0077] Pit 1244 will continue growing until etch self-terminates. Thedesigner can select a thickness of substrate 1202 and dimensions ofopenings 1206 and 1210 to permit this etching pattern, or anotherselected etching pattern.

[0078]FIG. 6i illustrates an interposer substrate 1252 (compare 1242)wherein the process has started with openings (compare 1206 and 1210)that do not have the same cross-dimension, as in the case discussed withrespect to FIG. 6h. Here it can be observed that pit 1254 (compare 1244)is wider and deeper than pit 1256 (compare 1246). FIG. 6i alsoillustrates the conductive material 1258 deposited onto the seed layers(not shown) in pits 1254 and 1256.

[0079] For certain resilient contact elements, as used in the interposer(or space transformer) embodiments of the present invention, a tipstructure can be fabricated as an end of each interconnect element. Asshown in FIG. 7a, tip structures 1320 (only two tip structures are shownin the view of FIG. 7a, for illustrative clarity) are aligned with thetips of the interconnection elements (contact element) 1332, usingstandard flip-chip techniques (e.g., split prism), and the assembly ispassed through a brazing furnace to reflow the joining material 1324,thereby joining (e.g., brazing) the prefabricated tip structures 1320 tothe ends of the interconnection elements 1332.

[0080] With respect to the fabrication of composite interconnectionelements having prefabricated tip structures, FIG. 7a, shows thefabrication method at a certain step prior to tip attachment. As shownin FIG. 7a, a silicon substrate or wafer 1302 is used as a sacrificialsubstrate. A layer of titanium 1308 is deposited on the top surface ofsubstrate 1302, and a layer of aluminum 1306 is deposited atop titaniumlayer 1308. A layer of copper 1310 is deposited atop aluminum layer1306. The aluminum layer serves as a release layer. Using a suitableetchant, the aluminum is preferentially (to the other materials of theassembly) etched away, and the silicon substrate 1302 simply “pops” off,resulting in an electronic component having interconnection elements,each having a prefabricated tip structure, as illustrated in FIG. 7b.Note that the joining material 1324 has reflowed as “fillets” 1325 onend portions of the interconnection elements 1332. In a final step ofthe process, the residual copper (1308) is etched away, leaving tipstructure 1320 with a desired contact metallurgy exposed for makingpressure connections to other electronic components. Alternatively, thebrazing (soldering) paste 1324 is omitted, and instead, a layer ofeutectic material (e.g., gold-tin) is plated onto the resilientinterconnection elements prior to mounting the contact tips (1320)thereto.

[0081] More detail regarding this tip attachment can be found in theU.S. Pat. No. 5,829,128, entitled “Method of Mounting Resilient ContactStructures to Semiconductor Devices.” It is within the scope of thisinvention that this technique can be used to join (e.g., braze orsolder) pre-fabricated tip structures to ends of non-resilientinterconnection elements, resilient interconnection elements, andcomposite interconnection elements, which are fabricated directly uponthe terminals of the semiconductor device. Other structures of andtechniques for fabricating tip structures using sacrificial substratesare disclosed in U.S. Pat. No. 5,994,152, entitled “FabricatingInterconnects and Tips Using Sacrificial Substrate,” issued on Nov. 30,1999, to Khandros et al., the disclosure of which is herein incorporatedby reference as though set forth in full.

[0082] In FIGS. 8a, 8 b and 8 c, contact tip structures that can beintegrated into the present interposer are shown. Further contact tipstructures and discussions and figures in association thereto arepresented in commonly assigned U.S. patent application Ser. No.08/819,464, entitled “Contact Tip Structures For MicroelectronicInterconnection Elements And Methods of Making Same,” filed on Mar. 17,1997, the disclosure of which is herein incorporated by reference asthough set forth in full. In FIG. 8a, a contact tip structure 1420 isshown to have a flat contact surface. These contact tips are shown asintegrated onto a “cobra” type buckling beam assembly adapted for use asinterposer structure. For many pressure contact applications, aspherical or very small surface area contact tip urging against anominally flat-surfaced terminal of an electronic component ispreferred. In other applications, the surface of the contact tipstructure will preferably have projections in the shape of a pyramid, atruncated pyramid, a cone, a wedge, or the like. Techniques forfabrication of such contact tip structures are presented in theaforementioned Ser. No. 08/819,464 application.

[0083] In FIG. 8b, one of the plurality of elongate contact tipstructures 1435 is shown with each structure having a projectingpyramid-shaped contact feature 1430 projecting from a surface thereof.It is this projecting contact feature that is intended to make theactual contact with a terminal (not shown) of an electronic component(not shown).

[0084] As shown in FIG. 8b, the pyramid-shaped contact feature 1430 maybe suitably polished (abraded) off, which will configure thepyramid-shaped feature as a truncated pyramid-shaped feature. Therelatively small flat end shape (e.g., a square measuring a few tenthsof a mil on a side, on the order of 1-10 microns), rather than a trulypointed end shape, will in many applications be sufficiently “sharp” tomake reliable pressure connections with terminals (not shown) ofelectronic components (not shown), and may tend to wear better than atruly pointed feature for making repeated (e.g., thousands of) pressureconnections to electronic components, such as might be expected in anapplication of the tipped interconnection elements of the presentinvention for a wafer-level contactor. The desired tip shape and featuredefinition will depend on the nature of both the contact tip and themating surface material and morphology. Design of these mating contactelements for optimum performance would have to be undertaken as part ofthe overall design exercise associated with building the interposerassembly itself.

[0085] As shown in FIG. 8c, in subsequent processing steps wherein acontact tip structure is fabricated (such as described in theaforementioned Ser. No. 08/819,464 patent application), one or more(four shown) “dimple” contact features 1418 project from the main bodyof the resulting contact tip structure 1425.

[0086] There are several variations of the “dimple” contact features1418. For example, resilient contact structures can be fabricated on thebase 1425 with tips of various shapes and distances from their bases.Alternatively, it is possible to reposition the contact structures onthe base 1425 by providing conductive traces so that the base is movedaway from a primary position to a desired location.

[0087] One useful embodiment of an interposer embodiment of the presentinvention having two different contact pad patterns, as describedhereinabove, is for mating with two different designs of components,i.e. components with different types of terminals. That is, in oneembodiment of the present invention, one surface of the interposer (suchas the “top” surface) includes a truncated pyramid contact pads and anopposite surface of the interposer (the “bottom surface) includescone-shaped contact pads. Any of the various types of contact pads, asrecited in the Ser. No. 08/819,464 application or known to those ofskill in the art, may be integrated into the various embodiments,discussed herein, of the present invention interposer.

[0088] Commonly assigned U.S. Pat. No. 5,829,128 (the “128 patent”),entitled “Method of Mounting Resilient Contact Structures ToSemiconductor Devices” and issued to Eldridge et al. on Nov. 3, 1998,discloses substrates with conductive material. The disclosure of thispatent document is herein incorporated by reference as though set forthin full. The '128 patent teaches exemplary substrates upon whichresilient interconnect elements are fabricated. In particular, in FIGS.8a-8 e, there is disclosed a silicon wafer used as the sacrificialsubstrate upon which tip structures are fabricated, and that tipstructures so fabricated may be joined (e.g., soldered, brazed) toresilient contact structures that already have been mounted to anelectronic component.

[0089] There is further disclosed in the '128 patent resilient contactstructures, as shown in FIG. 7a, wherein a “dead space” is used toposition an electrical component such as a decoupling capacitor. Thisconcept of piggybacking passive (such as capacitors and resistors)and/or active components between a substrate and a wafer and between asubstrate and a wafer contactor is integrated into an embodiment of thepresent invention, as shown in and discussed in connection with FIGS. 9aand 9 bherein.

[0090] In FIG. 9a, an interposer 1500 is shown connected to a plurality(two of many shown) of semiconductor devices (dies) 1502 and 1504 priorto singulating (separating) the devices from a semiconductor wafer(wafer not shown in FIG. 9a). A boundary between the two devices isindicated by the notch 1506. (The notch may or may not actually exist,and represents the position of a kerf (line) where the wafer will besawed to singulate the devices.)

[0091] In FIG. 9a, the interposer 1500 is further shown to include aninterposer substrate 1510 having a plurality of resilient contactelements 1508 disposed on a top surface of the substrate 1510 and aplurality of resilient contact elements 1536 disposed on a bottomsurface of the substrate 1510. The contact elements 1508 and 1536 arefabricated on the substrate 1510 in manners as described and/orincorporated by reference hereinabove. The wafer on which the devices1502 and 1504 are disposed includes terminals 1512 for being broughtinto mechanical and electrical contact with the contact elements 1508. Awafer contactor 1532 has disposed thereon a plurality of contact pads1534 for being brought into mechanical and electrical contact with thecontact elements 1536. The wafer on which the devices 1504 and 1502 aredisposed is brought to bear against the substrate 1510, or vice-versa,so that each of the contact pads 1512 effects a pressure connection witha corresponding one of the resilient contact elements 1508. Similarly,the wafer contactor 1532 is brought to bear against the substrate 1510,or vice-versa, so that each of the contact pads 1534 effects a pressureconnection with a corresponding one of the resilient contact elements1536. In this manner, a technique is provided for performing burn-in ofunsingulated semiconductor devices in wafer form.

[0092] The substrate 1510 can be of any of the materials discussedhereinabove, such as a printed circuit board (PCB), ceramic or silicon.

[0093] The wafer (devices 1502, 1504 and additional devices) is alignedwith the substrate 1510, using any suitable alignment means (such aslocating pins, not shown) so that each resilient contact element 1508bears upon a corresponding pad 1512. Similarly, the wafer contactor 1532is aligned with the substrate 1510 using any suitable alignment means sothat each resilient contact element 1536 bears upon a corresponding pad1534.

[0094] An important advantage accruing to the interposer 1500illustrated in FIG. 9a is that the resilient contact elements 1508 and1536 stand on their own (disassociated from one another), and can befabricated to extend to a significant distance from the substrate 1510.This is important, in that it provides an appreciable “dead space” bothbetween the resilient contact elements 1508 (and similarly between theresilient contact elements 1536) and between the opposing surfaces ofthe die (e.g., 1502) and the substrate 1510 (and similarly between theopposing surfaces of the wafer contactor 1532 and the substrate 1510).“Dead space” 1514 and “dead space” 1530 are disposed, as shown in dashedlines, on either surface of the substrate 1510. In many semiconductorapplications, it is beneficial to provide decoupling capacitors as closeto interconnections as possible. According to the present invention,there is ample space for decoupling capacitors to be located in theotherwise “dead spaces” 1514 and 1530. As depicted in FIG. 9a, suchdecoupling capacitors can be mounted to the wafer on which the die 1502and 1504 are disposed and/or to wafer contactor 1532. As is shown inFIG. 9b, the decoupling capacitors or other components may be connectedto substrate 1510 of interposer 1500. It should be appreciated thatpassive elements, other than capacitors, or in addition thereto, such asresistors, may be disposed in the “dead spaces” 1514 and 1530. Further,active elements may be disposed in the “dead spaces” 1514 and 1530.

[0095] For additional details of various types of contact elements(resilient and otherwise) for effecting pressure connections betweenelectronic components, such as done in connection with the presentinvention, the reader is directed to commonly assigned U.S. patentapplication Ser. No. 08/819,464 entitled “Contact Tip Structures forMicroelectronic Interconnection Elements,” filed on Mar. 17, 1997, thedisclosure of which is herein incorporated by reference as though setforth in full. Any of the various contact elements disclosed in thereferenced document can be used as interconnection elements, e.g.,interconnection elements 1006 and 1008 of FIG. 3.

[0096] In one embodiment of the interposer of the present invention,microelectronic contact structures are fabricated lithographically.Examples of such contact structures and fabrication thereof aredisclosed in detail in co-pending, commonly assigned U.S. patentapplication Ser. No. 09/032,473, referenced and incorporatedhereinabove. In particular, FIGS. 2L and 2M of the referencedapplication, which are presented herein as FIG. 10a and 10 b,respectively, illustrate an assembly 1600 in which a free-standingcontact structure 1660 is attached at its base end 1662 to an electroniccomponent 1602, the main body portion 1666 of structure 1660 ispositioned away from the surface of the electronic component 1602, andits tip end portion 1664 having a topography extending even farther fromthe level of the main body portion 1666. The sloped region 1663 of thebase end 1662 of the resulting contact structure 1660 is clearly visiblein these figures.

[0097] In FIGS. 10a and 10 b, contact element 1666 is mounted on anelectronic device comprising a silicon substrate 1602, a passivationlayer 1604 disposed on the surface of the silicon substrate 1602 and anopening 1606 extending through the passivation layer 1604 to themetallic pad 1608. Commonly, there is a plurality of such contact padson an electronic device.

[0098] Directly on top of substrate 1602, there is a passivation layer1604 covering the surface of substrate 1602 except for contact pad 1608.Contact pad 1608 is disposed over the surface of substrate 1602.

[0099] Next, a layer of conductive material 1610 is deposited on top ofthe passivation layer. Conductive layer 1610 is in contact with contactpad 1608. Passivation layer 1604 assists in bonding conductive layer1610 to passivation layer 1604.

[0100] Directly on top of conductive layer 1610, there is a seed layer1650, with a curved portion 1623. The seed layer 1650, when patterned,serves as a precursor for a contact structure to be fabricated on theelectronic device. The contact structure is in the form of an elongatemass of conductive material comprising a base end 1662, a main bodyportion 1666 and the tip end 1664. The main body portion 1666 of thecontact structure is in a plane, which is approximately parallel to thesurface of the substrate 1602. Contact structure 1660 is free-standingsecured by its base 1662 to substrate 1602, with its tip end free tomake contact with a terminal of another electronic device. Contactstructure 1660 reacts to applied forces by resiliently and/orcompliantly deflecting in any or all of the x, y and z axis. Furtherdetails of various types of contact elements and fabrication thereof areshown in the aforementioned U.S. patent application Ser. No. 09/032,473.

[0101]FIG. 11 shows another embodiment of the interposer in accordancewith the present invention. Interposer 1720 includes a plurality ofsolder balls 1704 disposed on the top surface of interposer substrate1710 for establishing contact between interposer 1720 and the terminalsor contact pads (not shown) of an electronic component 1700. Interposer1720 also includes a plurality of resilient contact elements 1706,disposed on the bottom surface of substrate 1710 for establishingcontact between interposer 1720 and the terminals or contact pads (notshown) of an electronic component 1702. In this manner, interposer 1720permits mechanical and electrical contact between electronic components1700 and 1702. Interposer substrate 1710 has disposed thereupon aplurality of compression stop structures 1708 for limiting compressionof contact elements 1706 upon pressure contact applied between component1700 and substrate 1710.

[0102]FIG. 12 shows yet another embodiment of the present inventionwherein an interposer 1750 has disposed on one surface thereof (in FIG.12, this surface is shown as the top surface of a substrate 1754) aplurality of spring contact elements 1752 that are fabricated usinglithographic techniques. Methods for fabricating such contact elementsare disclosed in commonly assigned U.S. patent application Ser. No.08/802,054, and its corresponding PCT application WO 97/43656, thedisclosure of which is herein incorporated by reference as though setforth in full. In this reference document, FIGS. 6a-6 c particularlyillustrate a technique for fabricating contact elements 1752.

[0103] In FIG. 12, contact elements 1752 bend to a compressed state in adirection as shown by directional arrow 1758 when the electroniccomponent 1762 is pressed towards the substrate 1754. Additionally,contact elements 1756 bend to a compressed state in a direction shown bydirectional arrow 1759 when the electronic component 1764 is pressedtowards the substrate 1754. The contact elements 1756 are shown to havea smaller pitch than the contact elements 1752. Components 1762 and 1764include contact pads 1770 and 1768, respectively, for connecting to thecontact elements 1752 and 1756.

[0104]FIG. 13 depicts an interposer in accordance with an embodiment ofthe present invention. Interposer 1800 comprises an interposer substrate1802, resilient contact elements 1816 and 1818, which are mounted onboth sides of the substrate 1802, as well as two sets of tile substrates1804, 1806 and 1808, and 1810, 1812 and 1814. One set of the tilesubstrates, tile substrates 1804, 1806 and 1808, are located atop ofinterposer substrate 1802, and the other set of the tile substrates,tile substrates 1810, 1812 and 1814, are located at the bottom ofinterposer substrate 1802.

[0105] The resilient contact elements (a plurality of resilient contactelements 1816, disposed on a top surface of the substrate 1802, throughcontact pressure with the top tiles, and a plurality of resilientcontact elements 1818, disposed on a bottom surface of the substrate1802, through pressure contact with the bottom tiles) connect the pairof tile substrates 1804 and 1810, and similarly connect the pairs 1806and 1812, and 1808 and 1814. Tile substrates 1804, 1806 and 1808 may bepart of an electronic component substrate such as a wafer (not shown inFIG. 13), including semiconductor devices or passive components.Similarly, tile substrates 1810, 1812 and 1814 may be an integral partof another electronic component, such as a wafer contactor, probetester, or the like. As the two layers of the tile substrates (1804 and1810, 1806 and 1812, and 1808 and 1814) are pushed towards each otherthe resilient contact elements 1816 and 1818 are compressed therebyexerting pressure and establishing electrical connection between thetiles substrates.

[0106] By way of further explanation, tile substrates, 1804, 1806 and1808, may be disposed on a wafer and tile substrates 1810, 1812 and 1814may be on a tester. Interposer 1800 permits the entire semiconductorwafer to be tested, probed or burned-in (generally referred to as“exercised”) at the same time. Multiple die sites, corresponding to thesubstrate tile 1804, 1806 and 1808, on a semiconductor wafer are readilyprobed by employing the substrate tiles 1810, 1812 and 1814 via theinterposer substrate 1802. In addition, substrate tiles on a tester,such as 1810, 1812 an 1814 may be arranged in order to optimize probingof an entire wafer.

[0107]FIG. 14 shows yet another embodiment of an interposer inaccordance with the present invention wherein two types of contactelements are employed on top and bottom surfaces of an interposer 1830for making contact to two electronic components. In FIG. 14, at the topsurface of the interposer substrate 1870, a plurality of contactelements 1861 and 1862 are affixed, for example, in the manner describedwith respect to FIG. 13c or FIG. 22b of commonly assigned PCTApplication No. PCT/US99/28597, entitled “Lithographic Contact Elements”filed on Dec. 1, 1999, which claims priority to U.S. patent applicationSer. No. 09/205,023 and “Lithographic Contact Elements,” filed on Dec.2, 1998, patent application Ser. No. 09/205,022 (the disclosures ofwhich are herein incorporated by reference as though set forth in full),so that tip portion ends 1872 and 1874 make pressure connections withterminals 1866 of electronic component 1864, such as a semiconductordevice, or an area of a semiconductor wafer (not shown) containing aplurality of semiconductor devices. Similarly, at the bottom ofsubstrate 1870, a plurality of contact elements are affixed, two ofwhich are shown to be 1840 and 1842. Tip structures 1854 and 1856 of thecontact elements 1840 and 1842 make pressure connections with terminals1858 of the electronic component 1850. Electronic component 1850 may bea wafer containing a plurality of semiconductor devices, a contactor, atest device or other electronic component described hereinabove. Thus,mechanical and electrical contact is established between the electroniccomponents 1850 and 1864.

[0108] It should be apparent from the foregoing discussion thatinterposers may be designed to interconnect a wide variety of electroniccomponents. By suitable choice of contact elements on both surfaces ofthe interposer, as can be appreciated, electronic components havingdifferent pitch, different lengths or different contact pads havingdiverse features may be interconnected using the apparatus and methodsof the present invention.

[0109] As shown in FIG. 15, interposer 1900 can be implemented inconjunction with a pressure activated contactor. As depicted in FIG. 15,interposer 1900 has contact elements 1902 and 1904 disposed on eachside, and the device under test is a complete semiconductor wafer 1906.Wafer 1906 is placed against a chuck 1908. A wiring substrate or layer1910 is positioned above interposer 1900. Wafer 1906 includes aplurality of contact pads 1912 and wiring substrate 1910 includes aplurality of terminals 1914. Pressure, as indicated by directional arrow1916 is utilized for enabling proper contact between interposer 1900 andwafer 1906, more specifically between contact elements 1904 and contactpads 1912, and between interposer 1900 and wiring substrate 1906, morespecifically, between contact elements 1902 and terminals 1914. Anexemplary pressure contact arrangement is discussed in commonly assignedU.S. patent application Ser. No. 09/376,759 entitled “ElectricalContactor, Especially Wafer Level Contactor, Using Fluid Pressure,”filed on Aug. 17, 1999, the disclosure of which is herein incorporatedby reference as though set forth in full. In this regard, it should beappreciated that various arrangements of stop structures, for example asdiscussed above in connection with FIGS. 3a and 3 b, may be implementedin the arrangement of FIG. 15.

[0110]FIG. 16 illustrates an instantiation of the system 1900 of thepresent invention, illustrating a number of features, which would beapplicable to a variety of instantiations of the technique of thepresent intention. These features are a plurality of ASICs 2006, mountedto an interconnection (support) substrate 2008, and a plurality of DUTs2002 connected to the ASICs 2006, through an interposer 2001, havingdouble-sided resilient contact elements as discussed hereinabove andindicated by the arrows 2003. A power supply 2018 provides power, viathe interconnection substrate 2008, via ASICs 2006 and via interposer2001, to the DUTs 2002 to power them up for operation. This isespecially useful for testing and also useful for burn-in.

[0111] Host controller 2016 provides signals to the ASICs 2006 via theinterconnection substrate 2008. Relatively few signals, for example aserial stream of data, need to be provided to each ASIC in order toindividually control the plurality (one of many shown) of ASICs 2006mounted to the interconnection substrate 2008. ASICs 2006 contact theresilient elements on the top surface of the interposer 2001 via thecontact pads 2020. In one embodiment of the present invention, ASICs2006 may be mounted adjacent to the contact pads 2020 thereby minimizingthe signal path between ASICs 2006 and DUTs 2002. However, it may not bealways possible to locate all the ASICs close to the contact pads 2020so that in an alternative embodiment of the present invention, the ASIC,being farther from the contact pads 2020, are wired to the contact pads2020.

[0112] The instantiation illustrated in FIG. 16 is an example of asystem for testing DUTs, for example, memory devices. Host controller2016 is connected to the plurality of ASICs 2008 through a data buswhich needs very few (e.g., four) lines: a line for data out (labeledDATA OUT), a line for data back (labeled DATA BACK), a line forresetting the ASICs (labeled MASTER RESET), and a line conveying a clocksignal (labeled CLOCK). All of the ASICs mounted to the interconnectionsubstrate are connected to these FOUR “common” lines that are connectedin the interconnection substrate to all of the ASICs. This illustratesthe simplicity in realizing (i.e., manufacturing) an interconnectionsubstrate (2008), which is adapted in use to test a plurality ofcomplicated electronic components (DUTs).

[0113] Power (labeled+V) and ground (labeled GROUND) connections aresimilarly easily dealt with in the interconnection substrate.Essentially, only two lines are required in the interconnectionsubstrate, which are preferably realized as planes (i.e., a power planeand a ground plane) in a multiplayer interconnection substrate. Moredetails may be found in commonly assigned PCT Publication No.WO/97,43656, entitled “Wafer Level Burn-in and Test”, the disclosure ofwhich is herein incorporated by reference as though set forth in full.

[0114] Communication, power and testing may be handled by a suitableASIC and control and support system, such as discussed in U.S. Pat. No.5,497,079, issued to Yamada et al. and owned by Mitsubishi, Inc. and PCTPublication No. WO/97,43656.

[0115] A problem associated with prior art techniques of powering up aplurality of DUTs is voltage drop through the interconnection substrate.This problem is overcome by the present invention by providing increasedvoltage to the ASICs (2006) and incorporating a voltage regulator(labeled VOLTAGE REGULATOR) in the ASICs.

[0116] One having ordinary skill in the art to which the presentinvention most nearly pertains will recognize that additionalfunctionality, not specifically illustrated, may readily be incorporatedinto the ASICs. For example, providing each ASIC with a unique addressand an address decoding function, to individualize its response to aserial stream of data coming form the controller 2016.

[0117] The operation and further details of a prior art system thatshares some of the same structures as disclosed in FIG. 16 is discussedin PCT Publication No. WO 97/43656. In FIG. 16, each ASIC can readilycommunicate over a large number of interconnection elements (springcontact elements) with the DUT to which it is connected through theinterposer 2001. Additionally, the ASICs resident on the interconnectionsubstrate can communicate multiples of the large number of connectionsbetween the ASICs and the DUTs.

[0118] In the event of use of ASICs on the tester side of the substrate,a 1:1 correspondence is typically required between the tester pads andthe DUT pads, unless a multiplexing circuitry is built into the DUTwafer. The system as described accomplishes this by using the ASCIsconnected directly to the WUT via the interposer, and then a smallnumber of connections from the ASICs to the tester board.

[0119] In the interposer of the present invention, if active componentsor other busing schemes are built into the interposer, the overall“connection count” can substantially be decreased, most notably in theinterconnection substrate. For example, an 8-inch wafer may contain 50016 Mb DRAMs, each having 60 bond pads, for a total of 30,000connections. Using the technique of the present invention, these 30,000connections are directly made between the ASICs and the DUTs; and, fromthe ASICs, through the interconnection (support substrate), back to thehost controller, e.g., power (2 lines) and a serial signal path (as fewas two lines, including the ground line from the power source). This isin marked contrast to techniques of any prior art which, even if it wereto use the ASICs of the present invention or similar instrumentality,would require connecting the ASICs via an interconnection substrate tomeans interconnecting the interconnection substrate to the DUTs. Thepresent invention completely eliminates this problem, and substantiallyreduces the numbers of nodes required on the interconnection substrate,by effecting connections directly between the ASICs and the DUTs.

[0120] Another aspect of the present invention is in the use of thevarious interposers presented and discussed herein as an in-circuitemulator (ICE) for use in testing the functionality of a product, suchas an integrated circuit, that is yet unavailable. In such a case, asknown to those skilled in the art, an ICE is use to create the samefunctions as those that would eventually be carried out by the productin development therefore expediting the testing process of the product.

[0121]FIG. 17 shows an interconnect assembly 2100 including a hostcontroller 2116, a power supply 2118 and a contactor system 2130 inaccordance with another embodiment of the present invention. Thecontactor system 2130 comprises base plates 2104 and 2104 a, aninterconnection substrate 2108, a plurality of ASICs 2106 a-2106 d, aplurality of DUTS 2102 a-2102 d and an interposer 2140. Interposer 2140may be any of the embodiments disclosed hereinabove. Interposer 2140comprises a substrate 2141 and resilient contact elements 2142.

[0122] The host controller 2116 is coupled to the interconnectionsubstrate 2108 through the interface line 2148 and the power supply iscoupled to the interconnection substrate 2108 through the transmissionline 2150. Guide pins 2112 allow the upper base plate 2104 a to belowered so that the ASICs 2106 a-2106 d come in contact with theresilient contact elements 2142 on the upper side of the substrate 2140.Resilient contact elements 2142 on the lower side of the substrate 2140rest against the DUTs 2102 a-2102 d. At this point electrical contact isestablished between the various ASICs and DUTs making it possible totest and probe various DUTs at the same time on the wafer-level.

[0123] Base plate 2104 a is stopped from moving too far and overcompressing the resilient contact elements 2142 by the compression stops2144. Additionally, compression stops may be disposed between 2140and/or 2106 and/or 2102 as discussed above in connection with FIG. 3b.

[0124] Power supply 2118 provides the power required for testing theDUTs and the host controller 2116 manages the various aspects of testingperformed on the DUTs, as discussed herein below.

[0125] In FIG. 18a, an interposer 2200 is shown comprising a substrate2202 and various beam-type resilient contact elements such as 2204. Themain feature of interposer 2200 is that the resilient contact elementsare not aligned so that different pitch lengths may be accommodated onthe two surfaces of the interposer. Shown in FIG. 18a is a smaller pitchlength 2206 on the bottom surface of the interposer and a longer pitchlength 2208 on the top surface of the interposer. In this way,interposer 2200 offers the flexibility of interconnecting differenttypes of devices. For example, one surface may be connected to a devicehaving a standard pitch pattern while the other surface may accommodatea device with a specific pitch.

[0126] In FIG. 18b, there is shown, an interposer assembly 2210 withvarious contact elements mounted on a substrate 2212. Substrate 2212includes three through-holes. Each through-hole represents a possiblevariation on the way contact elements may be mounted on the substrate2212. On the first through-hole 2214 is mounted two contact elements2218 and 2216 whose tips are offset as indicated by the arrow 2220.

[0127] At the second through-hole 2242 contact elements 2226 and 2228are mounted on the bases 2224 and 2232. The compression stops 2222 and2224 are mounted directly on top of the bases 2232 and 2230,respectively. In an alternative embodiment, the contact elements 2238and 2240 are mounted on the through-hole 2244. However, the compressionstops 2234 and 2236 are mounted away from the contact elements 2238 and2240, as shown in FIG. 18b. Hence, various ways of attaching contactelements to an interposer are possible which fall within the scope andspirit of the present invention.

[0128] In the foregoing specification, the present invention has beendescribed with reference to specific exemplary embodiments thereof. Itwill, however, be evident that various modifications and changes may bemade thereto without departing from the broader scope and spirit of theinvention as set forth in the appended claims. The specification anddrawings are, accordingly, to be regarded in an illustrative rather thanin a restrictive sense.

What is claimed is:
 1. An interposer comprising: a substrate havingfirst and second opposed sides with a first set of terminals on thefirst side, a second set of terminals on the second side, and a means ofelectrically interconnecting the terminals of the first and secondsides; a first set of resilient contact structures, each having aportion connected to a respective one of the terminals of the first setof terminals, a first contact region distant from the substrate, and anelongate section extending from the portion to the first contact region,the elongate section resiliently bending upon depression of the firstcontact region towards the substrate; and a second set of resilientcontact structures, each having a portion attached to a respective oneof the terminals of the second set of terminals, a contact regiondistant from the substrate, and an elongate section extending from theportion to the contact region, the elongate section resiliently bendingupon depression of the contact region towards the substrate, whereinupon depression of the first and second contact regions, the interposercauses electrical coupling of two devices.
 2. An interposer as recitedin claim 1 wherein said first set of resilient contact structures areoffset in position from said second set of resilient contact structures3. An interposer as recited in claim 1 further including componentsdisposed on said substrate.
 4. An interposer as recited in claim 3wherein said components are passive components.
 5. An interposer asrecited in claim 4 wherein said passive components are capacitors.
 6. Aninterposer as recited in claim 4 wherein said components are activecomponents.
 7. An interposer as recited in claim 1 wherein saidsubstrate is formed of silicon.
 8. An interposer as recited in claim 1wherein said substrate is formed of metallic material.
 9. An interposeras recited in claim 1 wherein said substrate is formed of organicmaterial.
 10. An interposer as recited in claim 1 wherein said substrateis formed of ceramic material.
 11. An interposer as recited in claim 1wherein said substrate includes power and ground planes.
 12. Aninterposer as recited in claim 1 wherein said substrate includesmultiple wiring layers.
 13. An interposer as recited in claim 1 whereinsaid first set of resilient contact structures are formedlithographically.
 14. An interposer as recited in claim 1 wherein saidsecond set of resilient contact structures are formed lithographically.15. An interposer as recited in claim 1 wherein said first set ofresilient contact structures are formed by bonding and plating.
 16. Aninterposer as recited in claim 1 wherein said second set of resilientcontact structures are formed by bonding and plating.
 17. An interposeras recited in claim 1 wherein an overtravel stop is disposed on saidfirst side of said substrate for controlling compression of said firstset of resilient contact structures upon depression of the first contactregion.
 18. An interposer as recited in claim 1 wherein a firstovertravel stop is disposed on said first side of said substrate forcontrolling compression of said first set of resilient contactstructures upon depression of the first contact region and furtherwherein a second overtravel stop is disposed on said second side of saidsubstrate for controlling compression of said second set of resilientcontact structures upon depression of the second contact region.
 19. Aninterposer as recited in claim 1 wherein said first and second set ofresilient contact structures comprise resilient spring structures. 20.An interposer as recited in claim 1 wherein said first set of contactstructures comprise solder balls.
 21. An interposer as recited in claim20 wherein said second plurality of contact structures compriseresilient spring structures.
 22. An interposer as recited in claim 1wherein said interposer is part of a wafer-level test assembly.
 23. Aninterposer as recited in claim 1 wherein contact elements of saidinterposer are formed lithographically.
 24. An interposer as recited inclaim 1 wherein through-holes are formed on said substrate.
 25. Aninterposer as recited in claim 1 wherein said substrate is substantiallyrigid.
 26. An interposer as recited in claim 1 wherein said substrate issubstantially flexible.
 27. A method for testing a wafer comprising:connecting a first side of an interposer having a first plurality ofresilient contact elements disposed thereon to the wafer; connecting asecond side of an interposer having a second plurality of resilientcontact elements disposed thereon to a wiring substrate; and providingsignals to the wiring substrate thereby causing testing of the wafer.28. A method for forming an interposer comprising: providing a substratehaving a first surface and a second surface, said second surface beingopposite of said first surface; forming a first plurality of contactelements on said first surface of said substrate; and forming a secondplurality of contact elements on said second surface of said substrate.29. A method as recited in claim 28 further including the step offorming through-hole terminals in said substrate.
 30. A method forperforming wafer-level burn-in and test of a plurality of semiconductordevices (DUTs) resident on a semiconductor wafer, comprising: providinga plurality of active electronic components having terminals on asurface thereof; and providing an interposer for effecting directelectrical connections between terminals of the plurality of DUTs andthe terminals of the active electronic components.
 31. An assembly forelectrically connecting a first electronic component to a secondelectronic component comprising: an interposer having a substrate havinga first surface and a second surface, said first surface having a firstset of resilient contact structures and said second surface having asecond set of resilient contact structures, the first and secondelectronic components having capture pads on their respective surfaces,configured to mate with corresponding first and second sets of resilientcontact structures; and a housing connected to secure the first andsecond electronic components to the interposer.
 32. A system for testinga wafer comprising: an interposer; a wiring layer; and means forconnecting the wafer to the wiring layer using the interposer therebycausing testing of the wafer.
 33. A system as recited in claim 32further including active components mounted to the wiring layer.
 34. Amethod for testing a semiconductor wafer comprising: providing awafer-under-test; providing a wiring layer being part of a wafer testsystem; and connecting an interposer having an upper surface and a lowersurface and having a plurality of resilient contact elements mounted oneach of said upper and lower surfaces, between the wafer-under-test andthe wiring layer, such connection being provided by the plurality ofresilient contact elements.
 35. A method for testing as recited in claim34 wherein providing a plurality of devices on the wafer-under-test andexercising the devices at elevated temperatures.